Electrical Test

What is Electrical Test?

The term Electrical Test (ET) is widely used across various industries, but what does it really mean?

Electrical Test is an evaluation of the parametric, functional, or timing performance of a component when electrical power is applied. Parametric tests typically involve a DC source and measures current or voltage. The current or voltage is measured to validate that the connection point has the expected voltage or current, hence creating the ‘TEST’. 

When the switch is closed in figure 1 current will flow causing the light to turn on. When the switch is not closed the light will turn off.
When the switch is open in figure 2 there will be no current flow

When performing Electrical Test on unpopulated PCB’s the process uses requirements that are documented on the fabrication drawing (master build drawing). These requirements will vary from part to part and should be set by the design engineer.

Unpopulated (Bare) PCB Electrical Test: This is a test that is run after the circuit board has been fabricated to make sure that all nets in the board have electrical connectivity. The test can also be performed in the fabrication process before the final solder resist coat is applied (solder mask). The test could also be performed on a single PCB layer or on a sequential lamination fabrication panel.

Electrical Test follows the base principals of Ohms Law. Ohm’s Law is a formula used to calculate the relationship between voltage, current and resistance in an electrical circuit.

V – Voltage 

 I – Current 

 R – Resistance

V= I x R

When Electrical Test is performed typically resistance is used as the base measurement so Ohms Law would be

When voltage is applied to the net current flows allowing the resistance of the PCB trace to be measured.

R= V / I

What is a short circuit?

The term Electrical Test (ET) is widely used across various industries, but what does it really mean?
Electrical Test is an evaluation of the parametric, functional, or timing performance of a component when electrical power is applied. Parametric tests typically involve a DC source and measures current or voltage. The current or voltage is measured to validate that the connection point has the expected voltage or current, hence creating the ‘TEST’.

What is an open circuit?

An open circuit is when the current flow is expected to be on a point, but the current flow has been interrupted by a break in the conductor. The Electrical Test process is designed to detect opens because the netlist knows what points should be connected. When an open or opens occur on an unpopulated PCB the boards can be repaired or reworked, or the PCB will be scrapped. Whereas, if an open occurs on an assembled board a jumper wire can be installed to correct the current flow.

What is a netlist?

The word netlist can be used in several different contexts, but perhaps the most popular is in the field of electronic design. In this context, a “netlist” describes the connectivity of an electronic design. Netlists usually convey connectivity information and provide nothing more than instances, nets, and perhaps some attributes. Netlists can be either physical or logical; either instance-based or net-based; and flat or hierarchical. The latter can be either folded or unfolded.

The flat file called IPC-356 by IPC International Inc (IPC) coming from the schematic drawing can be used to verify the PCB fabrication process by comparing the IPC-356 generated from the schematic drawing to the IPC-356 file generated from the PCB manufacturing data. If there are any discrepancies found they should be reviewed before the fabrication process is initiated.

When using a third-party Electrical Test provider this process can be enhanced by the provider using the original design files (Gerber, ODB++, DPF, etc) and comparing these files to the fabricators IPC-356 file.

Testable Points on a PCB

Electrical Test points on an unpopulated PCB can defined by any open surface finish area on the PCB that can conduct electricity. The Electrical Test process may utilize all open areas or perform some test point optimization to reduce production costs. The best practice to ensure the electrical integrity is met for your design is to clearly define how the test points should be assigned. If adequate test point coverage is not provided for in the design, the manufacturer may resort to other less expensive options.

All these areas may end up passing the minimum testing rules that you have set up for your layout, but they may not be the most optimum conditions for the final product. By taking the time to look at these areas from a functionality perspective, the final assembly will have the in-circuit test points (ICT) that will ensure a seamless final product. Clearly define the Electrical Test point coverage on your manufacture’s fabrication drawing.

Testable test points on a PCB should have a suitable conductive area that is free of non-conductive material like solder mask.

The above example shows a shift in the conductive area and may not be able to be tested on some fixed mechanical test types.

Possible Test Points on a PCB

Plated Through Hole (PTH)
Points A & B could have test points on them
Non-Plated Through Hole (NPTH)
Points C & D are not testable because there is no conductive material on the outer surface
Back Drill / Counter Bore
Point E is not testable because there is no conductive material
Point F could have test points
Hole 1- Micro via, point G could be tested
Hole 2- buried via, point H is not testable because the outer surface is not electrically conductive
Hole 3- PTH, points I & J could be tested
Surface Mount Technology (SMT), points K & L could be tested
Plated Slot 4, could be tested
Via hole 5, could be tested
Point N cannot be tested because there is not conductive material
Point M cannot be tested because there is not conductive material
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Interested?

We offer our services under 2 distinct frameworks: the OnDemand Solution and the Integrate Solution.
Depending on your needs, you can either outsource specific testing requirements or we can completely run your test area or test department on your behalf. Contact us now and we’ll find the best solution for your business.

KEVIN SYVRET

FINANCE DIRECTOR, NORTH AMERICA

Mr. Syvret joined Gardien Services Canada as Financial Controller in 2001 and assumed the role of Finance Director North America in 2007. Over the past 20 years, Mr. Syvret has held senior finance and accounting roles, including with Canadian Pacific Ltd and Sprint Inc.

NIRAJ PATEL

VICE PRESIDENT, GARDIEN NORTH AMERICA

Mr. Niraj Patel joined the company on a part time basis in 1993 while attending college full time. He worked in various positions until he graduated from the Centennial College Computer Systems Technology program, whereupon he was hired full time. He progressed through several testing and CAM department positions and was appointed North American CAM Manager in 1998. After 18 years with the company, Mr. Patel was promoted to Senior Vice President of Operations, Gardien Services Canada Inc. in 2011. In January, 2015 Mr. Patel became Vice President NA of the newly combined organizational unit North America which includes the Canada and USA.

TODD KOLMODIN

VICE PRESIDENT QUALITY, NORTH AMERICA

Mr. Todd Kolmodin, a native to the Pacific Northwest was born in Seattle Washington. At a young age he moved to the Portland Oregon area. In March of 1986 he graduated from ITT Technical Institute with a degree in Electronics Engineering Technology. Todd began his tenure in the Electrical Test field that same year.  Todd spent eight years working in an independent testing facility in Wilsonville Oregon where he built skills in all aspects of Electrical Test and Quality Assurance. 

Todd then spent a short term with Yamamoto Corporation on their Engineering staff covering PCB drill, finishing and Electrical Test before joining Probe Test Fixtures in 1995. His charge was CAM and Fixuring Manager.  Todd joined the Gardien Group in September 1998 continuing the same roll and taking on the responsibilities of Quality Manager for Oregon operations. In 2008 Mr. Kolmodin was promoted to Vice President Quality USA. In this position Mr. Kolmodin oversees and maintains the Gardien ITAR registration, ISO Multi-Site registration and multiple site Lab Suitability with the Defense Logistics Agency Land and Maritime. Now also maintaining the Gardien QMS system Todd now serves as Vice President Quality North America.

Mr. Kolmodin is also a published columnist and Technical Presenter with multiple appearances at the IPC Apex Expo Conferences in both San Diego and Las Vegas. 

ROLAND VALENTINI

CHIEF OPERATING OFFICER

Mr. Valentini was appointed COO in July 2010 after successfully serving as head of North American operations since 2005.

Roland has over ten years’ experience in the PCB industry, including sales, service, and project management at Atotech GmbH, Germany mainly relating to PCB plating equipment.
He has significant sales experience from his tenure at Mack Rides GmbH and headed up worldwide installations for Lurgi Bischoff GmbH.

Mr. Valentini received a Master’s Degree in Mechanical Engineering from the University of Mannheim, Germany.

RICHARD HORSMAN

EXECUTIVE CHAIRMAN

Prior to Richard joining Gardien in September 2014, he was Chairman/CEO of tool chain vendor Atego Group Systems Limited which was sold to PTC Inc.

Prior to joining Atego, Richard held a number of Executive and Non-Executive roles including Senior Independent Non-Executive Director of Plethora Solutions, an AIM listed Pharmaceutical Company and CEO of AIM listed Cybit Holdings plc. where he grew the company from inception to revenues of over 25 million and took the company through multiple acquisitions before managing a sale of the business to Francisco Partners.

Richard previously held a number of senior roles in the Software industry.

RICK MERAW

GROUP VICE PRESIDENT QUALITY

Mr. Meraw was appointed Group Vice President of Quality in Jan 2015 after successfully  serving as Senior Vice President of USA operations since 2011.  Prior to being responsible for USA operations Mr Meraw was responsible for Canadian operations since 2001.

Rick has over twenty years’ experience with Gardien Group and has various roles including, service technician, customer liaison, Quality manager, technical support, project management, and software design/ implementation.

In June 1992 he graduated with an Electronic Engineering Technologist degree, with honors from a local community college.

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ROLAND VALENTINI

CHIEF OPERATING OFFICER

Mr. Valentini was appointed COO in July 2010 after successfully serving as head of North American operations since 2005.

Roland has over ten years’ experience in the PCB industry, including sales, service, and project management at Atotech GmbH, Germany mainly relating to PCB plating equipment.
He has significant sales experience from his tenure at Mack Rides GmbH and headed up worldwide installations for Lurgi Bischoff GmbH.

Mr. Valentini received a Master’s Degree in Mechanical Engineering from the University of Mannheim, Germany.