What is a Flying Probe Test?
Flying probe test, as the name implies uses 2 or more test probes that move around and test each test point on the bare PCB. The test points are tested by the probes moving from test points to other test points as per instructions given by the specific software program that is written for the board under test. No customer fixture is required, so the cost of performing this test is economical, but the time to perform the test is longer than a test fixture. Hence, it is highly cost-effective for prototypes and low to mid-volume production.
Gardien was one of the first companies to develop the concept of a flying probe tester for use on bare boards. Flying Probes have become the GO TO standard for bare board testing where the main electrical parameter that is measured is the resistance between two points or nodes. However, continuously improving the flying probes allows enhanced tests including capacitance, embedded resistor, hipot, and low resistance (4-wire kelvin measurements.
Resistance Testing on a Flying Probe
Resistance testing on a flying probe follows the basic principal as defined on the ET (page link to it), the limitation being the number of probes used at a single moment. A minimum of two probes must be applied to the PCB to create current flow with one of the probes applying the voltage and the other probe being the sense probe.
IPC-9252 defines resistance testing as ‘Direct’, “A method of testing continuity where the circuit resistance is directly measured by imposing AC or DC current and measuring the resulting voltage by imposing an AC or DC voltage and measuring the resulting current.”
Direct test method: This test method for continuity test will apply the specified voltage and current to each net and measure the applicable end point nodes for the resistance value. If the resistance value is below the set threshold a “Pass” will be recorded.
Resistance Shorts Test on a Flying Probe
The principals of flying probes discontinuity test limit the ability to perform a full parametric shorts test on a PCB due to the test cycle times. A full parametric test requires every test point to be tested against every other test point.
Point 1 would need to be tested for a short using all ‘X’ points as the sense probe. This would equate to 11 test measurements.
All flying probe manufactures will default to some sort of a short test sequence to save processing time while still maintaining circuit integrity.
Direct test sequence:
Direct isolation test will not test each net against every other net for shorts, it will use some sort of adjacency methodology (See example line of site). The voltage and current is applied to one net and the other adjacent nets are measured for leakage current. The PCB industry has called the list of nets to be tested for shorts as adjacency. There are several different algorithm types that can be used to create the short test lists (adjacency) that are used to drive the flying probes to a specific location on the PCB to test that network for a short.
Example of Line of Site Adjacency
This type of shorts test tests the nets that lie within the line of sight of each other on the same layer. The nets must also lie within a fixed horizontal space (window size) in this example the window size has been set to 50 mils. The figure shows five traces that are side by side and are identified with A,B,C,D,& E. Net C in this example would be tested against nets B & D. Nets A & E would not be tested against net C because there are not adjacent to each other. Net A would not be checked against net B because it falls outside the horizontal distance window of 50 mils. Net D would be checked against net E because it is next to D and the horizontal distance is less than the 50 mils.
There is a low probability that the PCB manufacturing could have a short between trace A & B. If there was a physical short between A & B the flying probe would not detect this short because it was not found in the adjacency list. When testing any product on a flying probe there is a calculated risk that a short will not be detected because of the nets not being in the adjacency list.
Example of Z-Axis Adjacency
The z-axis adjacency takes all PCB layer to layer thickness and copper weight into account when calculating the adjacency. If the value of z-axis window is below the window size those nets will be tested using one of the exterior points of those nets.
In this example the z-axis window size is set to 10 mils.
|A-B||z-axis distance below value|
|A-C||z-axis distance below value|
|A-F||z-axis distance below value|
|D-C||z-axis distance below value|
|E-G||z-axis distance below value|
|C-F not tested because window size|
Indirect test sequence
This sequence uses something called signature comparison. Each net is not checked individually for continuity or isolation, instead each net is compared against a master set of values. In this sequence the Flying Probe has a netlist of the PCB in its required input format. This can be direct IPC or another format. For the Indirect Testing by Signature Comparison the first board will receive a more advanced test than subsequent boards. Indirect or Capacitance test will have the machine place a probe on the “reference” point that is a plane layer. The other probes will then process all the other test points in the PCB as “readers” or “antennae.” These values will then be placed in a temporary file. The machine will then do a full point-to-point Continuity test in resistive mode, checking all nodes against the set resistance threshold. Any violations will be reported as “Opens” and that net will be flagged in the temporary master as suspect. When the Continuity test is completed the Isolation test will be initiated using the Isolation threshold. Keep in mind the Adjacency window will be used as explained above. Any nets found in violation will be reported as “Shorted” and the nets will be flagged as suspect in the capacitance signature. The capacitance file will now be written as the master but in this case with possible suspect nets.
The second board is now tested. The machine will again do the signature (capacitance) gather but this time it will compare the readings to the previous master. All nets that report within the master capacitance values will be flagged as good and will not require any resistance verification. Any nets that violate the master will automatically be flagged for resistance verification. Also, on the second board if any nets were flagged as incorrect from the first board (that may have actually failed) they will automatically receive resistive Continuity and Isolation tests. These are to validate the nets against the original netlist. If these possible nets are now validated the capacitance master is then updated.
The third board is now tested. The machine again performs the signature (capacitance) gather. This time the master has all good values and if this board exhibits capacitive readings all within the master values it will pass with no resistive retests.
Example: Capacitance Measurements (Discharge Gather)
Limitations with Indirect Test Sequence
The indirect test sequence does not apply and measure a resistance to each net to determine the correct circuit integrity. If the design of this PCB requires this, the direct test sequence should be used. Another limitation exists with the Indirect sequence when it comes to the Electrical Test Certificate of Compliance. Most OEMs wish to see electrical test parameters noted on the C of C. With the Indirect sequence these parameters on the C of C are not possible as only nets RETESTED after the capacitive discharge gather will actually receive the desired test parameters. Only the first board tested will receive these requisites.
When testing PCBs, it can be quite confusing as to what sequence to use, what parameters are necessary for the Performance Class and what cost to associate in the build to weigh against the long-term reliability of the product. Design anomalies and capacitive cores can further cause stress in the once thought streamlined process. Understanding how the machines and sequences test the product up front may alleviate delays and unnecessary waste in what otherwise would have been conforming product and delivered on-time. From the OEM side the better understanding of how the sequences and parameters work against the product can better inform the manufacturer of possible anomalies in the final inspection process. If these are communicated up front, unnecessary delays can be omitted.
The Knowledge is more than PCB’s and the Software, it is complete process of hardware, software and humans.
Your Gardien Local Service Centre will have different makes and models of Flying Probes. Every machine type is tooled to test each part by a specific input file output from Ucam Software (link to Ucamco). The predetermined test sequence and parameters are programmed into the flying probes input file as well as Gardien’s proprietary job flow system called Ontrack (link to Ontrack). This creates a seamless and error free flow of information from the customer supplied data to the Service Floors at Gardien.
Gardien’s team is trained and qualified on all internal process as documented Quality Management System. The internal process has specific inputs for incoming, certified, and not good boards as well as descriptive educational programs on various board types, and surface finishes.
Gardien certifies each order processed with a Certificate of Compliance with details about how the order was processed, what specifications were used to certify the product, equipment used with calibration expiry date, team member who processed the order, quantity, and failure analysis.
Gardien strongly recommends that the test sequence and parameters are clearly stated on the manufacturing drawing or at a minimum agreed upon during the quoting or contract realization phase. In addition, any PCB sent to us for processing should have a unique identifier on each peace for electronic traceability.