What is Hipot?
Hipot or Dielectric Withstanding testing is designed to validate the insulation between a typical plane or potential layers. Typically, this is VCC and GND layers or combinations of split planes. A distinction must be made here regarding the test of dielectrics vs the high voltage test of individual nets.
Hipot by definition via TM-650 is the test of insulation of atypical potential layers, aka power and ground. When this test is indicated the industry provides 3 venues for accomplishing this.
Figure 7, shows a piece of foreign material between layer 3 and layer 4. The glass resin between layer 3-4 is reduced that has the potential of breaking down overtime. The standard ET test will not find this type of short because there would be no resistance between the traces on layer 3 & 4. The only way to reliably find this type of defect would be a Hipot test between these layers.
How the test works?
The probes can connect to one or multiple nets at once when using a dedicated fixture to wire the nets together. When the probes are connected to the nets this is typically called a hipot pair. The desired voltage is started at a lower value and increased slowly up to the required test voltage (called Ramp Time). Once the test voltage is reached it is held there for a fixed period (called Dwell Time). The sense probe is always on looking to detect current flow, if current flow is detected and exceeds the threshold the test will fail. If no current flow is detected or the current detected is below the threshold the test will pass.
- Voltage – The potential to apply to the test. This could be both AC or DC as indicated
- Ramp Time – The time in seconds to bring the voltage to the required level
- Dwell Time – The time to maintain the voltage at the required level
- Sense Current – The value of current measure if exceeded the test will fail.
IPC recommends Ramp time to be 1 second/per 100V required with a recommended dwell time of 30 seconds.
- Place probes on the PCB.
- Turn voltage on at the lowest value and turn on the sense probe.
- Ramp voltage up 1 volt per second.
- Once the required voltage is reached, start the dwell time.
- If dwell time has expired, this pair has passed. The pair is finished move to the next pair.
At any time if a sense current exceeds the threshold the test fails.
Ex: 500V, 30 second dwell time
Green area is the voltage ramp time in this example 100V per second for a total of 5 seconds.
Gold area is the voltage hold time so the analyser the pair to ensure no stray current is found.
In this example the voltage is held for 30 seconds.
Manual hipot is simply laying the pcb on a surface that is nonconductive and holding the probes on the two nets that are required to be tested. When the probes are on the pcb pads the analyser test sequence is started, the sequence is completed the probes can be removed.
Over time heave manual probes could be used to hold the probe on the pad so the operator has no concerns about electrical shock. See the below example.
The manual test will get the test performed for small volumes, but medium and large volumes should utilize Flying Probe or Fixture Hipot test.
Flying Probe Hipot
The test is fully automated by using a Flying Probe Machine. The pairs are programmed in an adjacency method for the Flying Probe. With the proper programming interface to the Hipot Analyzer this test can reduce much time. In this case the operator only needs to load the board to the machine and initiate the test. The number of pairs requiring test is irrelevant as the machine performs all tests automatically. This allows the operator to perform other tasks as indicated to improve efficiency of the overall operation.
The advantage is pairs are quickly analysed and uniform probe pressure is used for each paid.
The disadvantage would be cycle times increase proportional to the number of pairs tested.
An enhancement to this process is Hi-Pot fixture testing. This incorporates a drilled fixture that is wired for the pairs requiring test. The operator only needs to place the board on the fixture and initiate the test. The analyser then automatically sequences between the pairs and the operator does not need to move probes.
Fixtures have an advantage of performing the test quickly compared to Manual or Flying Probe test. The use of manual or automated switching devices enhances the test even further. The adoption of automated fixture testers could also be used to for high volume parts.
The disadvantage of a fixture hipot test is that it is expensive to produce the fixture.
Items that will be in the notes of the fabrication drawings related to hipot testing:
- Specific references to Insulation, Dielectric or HiPot test all mean HiPot
- References to Test Methods Manual IPC TM-650
- Specific Voltage requirements
- Ramp Time and Dwell Time
- Tables on the Fab Drawing indicating which “Nets” or “Pairs” require HiPot testing
- Dielectric or HiPot test using Condition A or Condition B (See TM-650)
Remember that in most cases the notes on the Fab Drawing will override industry specifications
- Dielectric Test is Plane Layers Insulation (layer to layer)
- Dielectric or Hipot is related to only the insulation test of cores between plane layers.
- Does NOT include Net to Net Testing.
- This designation should not be synonymous with high voltage testing of individual nets.
- This has been an industry problem on Master Drawings with regards to voltage requirements.
For high voltage tests on specific nets (Military common with this) it should be designated specifically as High Voltage Tests and not Hi-Pot. There is a difference.
Detect these defects before they hunt you later.
Why Gardien’s Solution?
Your Gardien Local Service Centre will offer different types of hipot services. Each hipot is specifically tooled/fixtured to test a part using a combination of UCAM and Fixgen Software (link to Ucamco). The Fixture production process is controlled to ensure an on-time fixture delivery in Gardien’s proprietary job flow system called Ontrack (link to Ontrack). This creates a seamless and error free flow of information from the customer supplied data to the Service Floors at Gardien.
Gardien’s team is trained and qualified on all internal process as documented Quality Management System. The internal process has specific inputs for incoming, certified, and not good boards as well as descriptive educational programs on various board types, and surface finishes.
Gardien certifies each order processed with a Certificate of Compliance with details about how the order was processed, what specifications were used to certify the product, equipment used with calibration expiry date, team member who processed the order, quantity, and failure analysis.
Gardien strongly recommends that the test sequence and parameters are clearly stated on the manufacturing drawing or at a minimum agreed upon during the quoting or contract realization phase. In addition, any PCB sent to us for processing should have a unique identifier on each peace for electronic traceability.
We offer our services under 2 distinct frameworks: the OnDemand Solution and the Integrate Solution.
Depending on your needs, you can either outsource specific testing requirements or we can completely run your test area or test department on your behalf. Contact us now and we’ll find the best solution for your business.